Fast Hardware Implementations of Static P Systems

In this article we present a simulator of non-deterministic static P systems using Field Programmable Gate Array (FPGA) technology. Its major feature is a high performance, achieving a constant processing time for each transition. Our approach is based on representing all possible applications as words of some regular context-free language. Then, using formal power series it is possible to obtain the number of possibilities and select one of them following a uniform distribution, in a fair and non-deterministic way. According to these ideas, we yield an implementation whose results show an important speed-up, with a strong independence from the size of the P system.Ministry of Science and Innovation of the Spanish Government under the project TEC2011-27936 (HIPERSYS)European Regional Development Fund (ERDF)Ministry of Education of Spain (FPU grant AP2009-3625)ANR project SynBioTI

Digital Data Processing Peripheral Design for an Embedded Application based on the Microblaze Soft Core

In this paper we present a design of a peripheral for MicroBlaze soft core processor as part of a R+D project carried out in cooperation with three different companies. The objective of the project consisted in the development of an embedded system with a SoC implemented on a FPGA custom-designed board. This work addresses the design of a Digital Data Processing peripheral included as a part of the target SoC application, that process digital signals via the digital inputs on a proposed board. Peripheral functionality is configurable for each digital signal independently and is configured from the software running on the MicroBlaze processor core.Ministerio de Educación y Cultura TEC2007-61802/MICJunta de Andalucía EXC-2005-TIC-102

Automated performance evaluation of skew-tolerant clocking schemes

In this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes are the well known master–slave clocking scheme (MS) and two schemes developed by the authors: Parallel alternating latches clocking scheme (PALACS) and four-phase parallel alternating latches clocking scheme (four-phase PALACS). In order to evaluate the timing performance, the authors introduce algorithms to obtain the clock waveforms required by a synchronous sequential circuit. Separated algorithms were developed for every clocking scheme. From these waveforms it is possible to get parameters such as the non-overlapping time and the clock period. They have been implemented in a tool and have been used to compare the timing performance of the clocking schemes applied to a simple circuit. To analyse the power consumption the authors have electrically simulated a simple circuit for several operation frequencies. The most remarkable conclusion is that it is possible to save about 50% of the power consumption of the clock distribution network by using PALACS.Ministerio de Ciencia y Tecnología TEC 2004-00840/MI

Implementation of a FFT/IFFT Module on FPGA: Comparison of Methodologies

In this work, we have compared three different methodologies for the implementation of a FFT/IFFT module on FPGA: VHDL coding (VC), System-level tools at RT level (STR), and System-level tools at macroblock level (STM). In terms of resource usage and operation frequency, STM has obtained interesting results, although it has an important restriction about internal data width which produces a mean output error of 2.1%. VC and STR become a more general alternative that yields to a lower mean error (1.0%). Thus, we propose to combine VC and STR in order to facilitate the design process as well as allow designers to maintain total control over the module internal architecture and obtain an efficient structure

Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation

Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most critical features of the synchronization protocols in hardware and the synchronization algorithms in software. In this paper, a new clock discipline algorithm for hardware implementation is presented, allowing for full hardware implementation of synchronization systems. Measurements on field-programmable gate array prototypes show a fast convergence time (below 10 s) and a high accuracy (1 μs) for typical configuration parameters.Ministerio de Educación y Cultura HIPER TEC2007-61802/MI

Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)

12th International Workshop, PATMOS: : International Workshop on Power and Timing Modeling, Optimization and Simulation, Seville, Spain, September 11–13, 2002 ISBN: 978-3-540-44143-4In previous papers we have presented a very accurate model that handles the generation and propagation of glitches, which makes an important headway in logic timing simulation. This model is called Delay Degradation Model (DDM). Characterizing DDM completely also implies the characterization of the normal propagation delay. In this paper, we propose a simple heuristic model that includes its dependence on the output load and the input transition time. We have tested this model and found a mean deviation lower than 4%. Also, we present a characterization process for this model that is fully integrated into AUTODDM without affecting the total simulation time needed to characterize a standard cell.Ministerio de Ciencia y Tecnología MODEL TIC 2000-1350Ministerio de Ciencia y Tecnología VERDI TIC 2002-228

Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level

This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current model and a current curve generation algorithm that is implemented as an attached module to a logic simulator under development called HALOTIS. The implementation is aimed at efficiency and overall estimations, making it suitable to switching noise evaluation and current peaks localisation. Simulation results and comparison to HSPICE confirm the usefulness and efficiency of the approach.Ministerio de Ciencia y Tecnología MODEL project TIC 2000-1350Ministerio de Ciencia y Tecnología VERDI project TIC 2002-228

Building a basic membrane computer

In this work, we present the building of two well-known membrane com- puters (squares generator and divisor test). Although they are very basic machines they present problems common to every P system (competition, parallel execution of rules, membrane dissolution, etc.) that have to be solved in order to get real emulations for them. The presented designs mimic the systems operation in a realistic way, by achieving both maximum parallelism and non-determinism, and demonstrating for the rst time that a membrane computer can actually be built in silico. Our architectures fully emu- late the membranes behaviour yielding to a performance of one transition per clock cycle, supposing a real physical realization of the mentioned machines

Sistemas de control de grupos de prácticas. Aplicación al ámbito docente del Departamento de Tecnología Electrónica de laUniversidad de Sevilla

En este trabajo, se presenta un sistema automático, basado en web, orientado a facilitar la organización de prácticas de laboratorio en asignaturas con elevado número de alumnos. Se caracteriza por permitir tanto su utilización como su administración mediante browser, cumplir con los necesarios requisitos de seguridad, y soportar acceso a los datos de forma concurrente. Además, la implantación se ha realizado mediante software de libre distribución lo que demuestra, una vez más, la viabilidad e idoneidad de este tipo de plataformas

Open Development Platform for Embedded Systems

Ministerio de Economía y Competitividad TEC2011-2793